U-Bootのソースを読んでみる(1)

CPUはarmv7アーキテクチャのブートコードを読んでみる。

始まりは
arch/cpu/armv7/start.S
からっぽい。
http://detail.chiebukuro.yahoo.co.jp/qa/question_detail/q1237585277

[arch/cpu/armv7/start.S]

 38 .globl _start
 39 _start: b   reset
 40     ldr pc, _undefined_instruction
 41     ldr pc, _software_interrupt
 42     ldr pc, _prefetch_abort
 43     ldr pc, _data_abort
 44     ldr pc, _not_used
 45     ldr pc, _irq
 46     ldr pc, _fiq

[start.S]

126 reset:
127     bl  save_boot_params
128     /*
129      * set the cpu to SVC32 mode
130      */
131     mrs r0, cpsr
132     bic r0, r0, #0x1f
133     orr r0, r0, #0xd3
134     msr cpsr,r0
135 
136 /*
137  * Setup vector:
138  * (OMAP4 spl TEXT_BASE is not 32 byte aligned.
139  * Continue to use ROM code vector only in OMAP4 spl)
140  */
141 #if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
142     /* Set V=0 in CP15 SCTRL register - for VBAR to point to vector */
143     mrc p15, 0, r0, c1, c0, 0   @ Read CP15 SCTRL Register
144     bic r0, #CR_V       @ V = 0
145     mcr p15, 0, r0, c1, c0, 0   @ Write CP15 SCTRL Register
146 
147     /* Set vector address in CP15 VBAR register */
148     ldr r0, =_start
149     mcr p15, 0, r0, c12, c0, 0  @Set VBAR
150 #endif
151 
152     /* the mask ROM code should have PLL and others stable */
153 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
154     bl  cpu_init_cp15
155     bl  cpu_init_crit
156 #endif
157 
158 /* Set stackpointer in internal RAM to call board_init_f */
159 call_board_init_f:
160     ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
161     bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
162     ldr r0,=0x00000000
163     bl  board_init_f

CPUをSVC32(スーパバイザモード)にする
ベクターをセット(SCTLRレジスタを設定)？
mrc,mcrはコプロセッサとのやりとりをする命令らしい。

The SCTLR characteristics are:

Purpose
    Provides control and configuration of:
        memory alignment and endianness,
        memory protection and fault behavior
        MMU and cache enables
        interrupts and behavior of interrupt latency
        location for exception vectors
        program flow prediction.

VBAR = Vector Base Address Register

The VBAR characteristics are:

Purpose
    Provides the exception base address for exceptions that are not handled in monitor mode.

reset:
...
154     bl  cpu_init_cp15
155     bl  cpu_init_crit

311 /*************************************************************************
312  *
313  * cpu_init_cp15
314  *
315  * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
316  * CONFIG_SYS_ICACHE_OFF is defined.
317  *
318  *************************************************************************/
...
348 /*************************************************************************
349  *
350  * CPU_init_critical registers
351  *
352  * setup important registers
353  * setup memory timing
354  *
355  *************************************************************************/

cpu_init_crit内で

363     b   lowlevel_init       @ go setup pll,mux,memory

ボード側へ初期化処理が移る。
[lowlevel_init.S]

ENTRY(lowlevel_init)
    /*
     * Setup a temporary stack
     */
    ldr sp, =CONFIG_SYS_INIT_SP_ADDR
    bic sp, sp, #7 /* 8-byte alignment for ABI compliance */

    /*
     * Save the old lr(passed in ip) and the current lr to stack
     */
    push    {ip, lr}

    /*
     * go setup pll, mux, memory
     */
    bl  s_init
    pop {ip, pc}
ENDPROC(lowlevel_init)

arch/arm/cpu/armv7/zynq
を追って見る。
[arch/arm/cpu/armv7/zynq/cpu.c]

inline void lowlevel_init(void) {}

void reset_cpu(ulong addr)
{
    while (1)
        ;
}

特に何もしてない!!

ということは、

reset:
...
163     bl  board_init_f

かな。
[arch/arm/lib/spl.c]
にboard_init_fを発見。
あれ、でも
[arch/arm/lib/board.c]
にもboard_init_fを発見。
・・・board.cを採用！
[arch/arm/lib/board.c]

261 void board_init_f(ulong bootflag)